S-9.2.1 Extended Packet Formats For Digital Command Control

Original

Original Version: July 2012

Note

This document received approval from the NMRA Board of Trustees in July 1995, March 1997, July 2003 and January 2006. Changes since the last approved version are indicated by change bars on the left or right side of the document. Minor edit changes made to agree with S-9.2.2 Configuration Variables For Digital Command Control. Edit changes made July 2009. Changed to Standard July 2012.

The NMRA Communications Standard for Digital Communications (S-9.2) provides a minimal, basic packet format required for interoperability. This Standard provides Extended Packet Formats that provide the framework to enable realistic operations to occur. These formats adhere to the general packet format as defined in S-9.2. While the baseline packet has a length of 3 data bytes separated by a 0 bit, a packet using the extended packet format definition may have a length of between 3 and 6 data bytes each separated by a 0 bit.

Format Definitions

Within this Standard, bits within the address and data bytes will be defined using the following abbreviations. Individual bytes within a specific packet format are separated by spaces. Bytes which are within square [] brackets can occur one or more times as necessary. Bits are numbered from right to left with bit 0 (the right most bit) being the least significant bit (LSB) and bit 7 (the left most bit) being the most significant bit (MSB).

Symbol	Description
A	Address bit
0	Bit with the value of 0
1	Bit with the value of 1
U	Bit with undefined value either a 1 or a 0 is acceptable
B	Bit position / address
C	Instruction type fields
F	Flag to determine instruction implementation
L	Low order binary state control address
H	High order binary state control address
S	Decoder sub address
V	CV address bit
D	data
X	Signal head aspect data bit
E	Error detection bit

A: Address Partitions

The first data byte of an Extended Packet Format packet contains the primary address. In order to allow for different types of decoders this primary address is subdivided into fixed partitions as follows.

Address	Description
00000000 (0)	Broadcast address
00000001-01111111 (1-127)	Multi function decoders with 7 bit addresses
10000001-10111111 (128-191)	Basic accessory decoders with 9 bit addresses and extended accessory decoders with 11 bit addresses
11000001-11100111 (192-231)	Multi function decoders with 14 bit addresses
11101000-11111110 (232-254)	Reserved for future use
11111111 (255)	Idle packet

B: Broadcast Command for Multi-Function Digital Decoders

The format for this packet is:

preamble 0 00000000 0 instruction-bytes 0 EEEEEEEE 1

Instructions addressed to “broadcast address” 00000000 must be executed by all Multi Function Digital Decoders. The single instruction has the same definition as defined by the Multi Function Digital Decoder packet and can be one, two, or three bytes in length depending on the instruction. Digital Decoders should ignore any instruction they do not support. The manufacturer must document which broadcast commands a decoder supports.

C: Instruction Packets for Multi Function Digital Decoders

The format for this packet is:

preamble 0 [ AAAAAAAA ] 0 instruction-bytes 0 EEEEEEEE 1

Multi Function Digital Decoders are used for the purpose of controlling one or more motors and/or accessories. The packet format used to control these devices consists of between 3 and 6 bytes where the first bytes are address bytes followed by one or two instruction bytes and ended by an error control byte.

The first address byte contains 8 bits of address information. If the most significant bits of the address are 11 and the remaining bits are not 111111, then a second address byte must immediately follow. This second address byte will then contain an additional 8 bits of address data. When 2 bytes of address information are present they are separated by a 0 bit. The most significant bit of two byte addresses is bit 5 of the first address byte. (bits 6 and 7 having the value of 1 in this case).

Instruction-bytes are data bytes used to send commands to Multi Function Digital Decoders. Although it is unlikely that all Digital Decoders will implement all instructions, it is important that if they support packets with more than a single instruction, they can sufficiently parse the packet to be able to recognize if a byte is a new instruction or the second byte of a previous instruction.

Each instruction (indicated by instruction-bytes) is defined to be:

instruction-bytes = CCCDDDDD,
                    CCCDDDDD 0 DDDDDDDD, or
                    CCCDDDDD 0 DDDDDDDD 0 DDDDDDDD

Each instruction consists of a 3-bit instruction type field followed by a 5-bit data field. Some instructions have one or two or three additional bytes of data. The 3-bit instruction type field is defined as follows:

CCC	Description
000	Decoder and consist control instruction
001	Advanced operation instructions
010	Speed and direction instruction for reverse operation
011	Speed and direction instruction for forward operation
100	Function group one instruction
101	Function group two instruction
110	Future expansion
111	Configuration variable access instruction

The last byte of the packet is the Error Detection Byte, which is calculated the same as is done in the baseline packet using all address, and all instruction bytes (see S-9.2).

Decoder and Consist Control Instruction (000)

With the exception of the decoder acknowledgement function (00001111), only a single decoder and consist control instruction may be contained in a packet.

Decoder Control (0000)

The decoder control instructions are intended to set up or modify decoder configurations.

The format for this packet is:

instruction-bytes = 0000CCCF or
                    0000CCCF DDDDDDDD

This instruction (0000CCCF) allows specific decoder features to be set or cleared as defined by the value of D (1 indicates set). When the decoder has decoder acknowledgement enabled, receipt of a decoder control instruction shall be acknowledged with an operations mode acknowledgement.

CCCD	Description
0000	Digital decoder reset
0001	Hard reset
001D	Factory test instruction
010D	Reserved for future use
011D	Set decoder flags
100D	Reserved for future use
101D	Set extended address (CV 29 bit 5)
110D	Reserved for future use
111D	Decoder acknowledgement request

Digital Decoder Reset

A Digital Decoder Reset shall erase all volatile memory (including and speed and direction data), and return to its initial power up state as defined in S-115 9.2.4 section A. Command Stations shall not send packets to addresses 112-127 for 10 packet times following a Digital Decoder Reset. This is to ensure that the decoder does not start executing service mode instruction packets as operations mode packets (Service Mode instruction packets have a short address in the range of 112 to 127 decimal.)

Hard Reset

Configuration Variables 29, 31 and 32 are reset to its factory default conditions, CV 19 is set to 00000000 and a Digital Decoder reset (as in the above instruction) shall be performed.

Factory Test Instruction

This instruction is used by manufacturers to test decoders at the factory. It must not be sent by any command station during normal operation. This instruction may be a multi-byte instruction.

Set Decoder Flags

Note

This instruction is under re-evaluation by the NMRA DCC Working Group. Manufacturers should contact the NMRA DCC Coordinator before implementing this instruction.

Set Decoder Flags is an expanded decoder control function that allows for the command station to turn on or off flags within a specific decoder or within a group of decoders.

The format for this packet is:

instruction-bytes = 0000011D CCCC0SSS

SSS is the decoder’s sub-address. This allows for up to 7 decoders to share the same decoder primary address, yet have certain functions (such as Configuration Variable Access Instructions) be performed on an individual basis. If SSS = 000 then the operation affects all decoders within the group. The decoder sub-address is defined in CV15.

CCCC is defined in the following table:

CCCC	Meaning	Action	Scope
0000	Disable 111 Instructions [1]	Instruction is ignored for all sub addresses.	Until next Digital Decoder Reset Packet is received.
0100	Disable Decoder Acknowledgement Request Instruction	Acknowledgement and Address are not transmitted in response to a Decoder Acknowledgement Instruction for all sub addresses.	Until power is removed long enough to power down the decoder.
0101	Activate Bi-Directional Communications	B-Directional Communications are enabled per CVs (See note below).	Permanent (sets CV 29 (or 541), bit 3) or internal Flag if sent to Consist Address.
1000	Set Bi-Directional Communications	Bi-Directional communications are enabled for specified sub address; all other sub addresses are disabled. (Not valid at Consist Address).	Permanent (sets CV 16, bit 0)
1001	Set 111 Instruction	Enables 111 Instructions for specified subaddress, all other sub addresses are disabled. (Not valid at Consist Address).	Permanent (sets CV 16, bit 1)
1111	Accept 111 Instructions	All multi-CV programming instructions are now valid.	One-Time

Note

This command is valid at both the decoder’s base address and (if active) the consist address. If sent to the base address, the command affects both the base address and the active consist address (if any). If sent to the consist address, and D = 0 this command has no effect on the base address. If sent to the consist address, and D = 1 this command has no effect.

Consist Control (0001)

This instruction controls consist setup and activation or deactivation.

When Consist Control is in effect, the decoder will ignore any speed or direction instructions addressed to its normal locomotive address (unless this address is the same as its consist address). Speed and direction instructions now apply to the consist address only.

Functions controlled by instruction 100 and 101 will continue to respond to the decoders baseline address. Functions controlled by instructions 100 and 101 also respond to the consist address if the appropriate bits in CVs 21, 22 have been activated.

By default all forms of Bi-directional communication are not activated in response to commands sent to the consist address until specifically activated by a Decoder Control instruction. Operations mode acknowledgement and Data Transmission applies to the appropriate commands at the respective decoder addresses.

The format of this instruction is:

instruction-bytes = 0001CCCC 0 0AAAAAAA

A value of 1 in bit 7 of the second byte is reserved for future use. Within this instruction CCCC contains a consist setup instruction, and the AAAAAAA in the second byte is a seven bit consist address. If the address is 0000000 then the consist is deactivated. If the address is non-zero, then the consist is activated.

If the consist is deactivated (by setting the consist to 0000000), the Bi-Directional communications settings are set as specified in CVs 26-28.

When operations-mode acknowledgement is enabled, all consist commands must be acknowledged via operations-mode acknowledgement.

The format for CCCC shall be:

CCCC	Description
0010	Set the consist address as specified in the second byte, and activate the consist. The consist address is stored in bits 0-6 of CV 19 and bit 7 of CV 19 is set to a value of 0. The direction of this unit in the consist is the normal direction. If the consist address is 0000000 the consist is deactivated.
0011	Set the consist address as specified in the second byte and activate the consist. The consist address is stored in bits 0-6 of CV 19 and bit 7 of CV 19 is set to a value of 1. The direction of this unit in the consist is opposite its normal direction. If the consist address is 0000000 the consist is deactivated.
Others	Reserved for future use.

Advanced Operations Instruction (001)

These instructions control advanced decoder functions. Only a single advanced operations instruction may be contained in a packet.

The format of this instruction is:

001CCCCC 0 DDDDDDDD

CCCCC	Description
11111	128 Speed Step Control
11110	Restricted Speed Step Instruction
11101	Analog Function Group

128 Speed Step Control

Instruction 11111 is used to send one of 126 Digital Decoder speed steps. The subsequent single byte shall define speed and direction with bit 7 being direction (1 is forward and 0 is reverse) and the remaining bits used to indicate speed. The most significant speed bit is bit 6. A data-byte value of U0000000 is used for stop, and a data-byte value of U0000001 is used for emergency stop. This allows up to 126 speed steps. When operations mode acknowledgement is enabled, receipt of a 128 Speed Step Control packet must be acknowledged with an operations mode acknowledgement.

Restricted Speed Step Instruction

Instruction 11110 is used to restrict the maximum speed of a decoder. Bit 7 of the data byte (DDDDDDDD above) is used to enable (0) or disable (1) restricted speed operation. Bits 0-5 of the Data byte are the Speed Steps defined in S-9.2 [2]. When operations mode acknowledgement is enabled, receipt of a Restricted Speed Instruction must be acknowledged with an operations mode acknowledgement.

Analog Function Group

The format of this instruction is:

001CCCCC 0 VVVVVVVV 0 DDDDDDDD

where VVVVVVVV is Analog Function Output (0-255) and DDDDDDDD is Analog Function Data (0-255). Analog Output use 00000001 Volume Control.

All other values of VVVVVVVV are reserved. This function must not be used to control the speed of a mobile decoder.

When operations mode acknowledgement is enabled, receipt of a Analog Function Group Instruction must be acknowledged with an operations mode acknowledgement.

The remaining 29 instructions are reserved for future use.

Speed and Direction Instructions (010 and 011)

These two instructions have these formats

010DDDDD Reverse Operation
011DDDDD Forward Operation

A speed and direction instruction is used send information to motors connected to Multi Function Digital Decoders. Instruction 010 indicates a Speed and Direction Instruction for reverse operation and instruction 011 indicates a Speed and Direction Instruction for forward operation. In these instructions the data is used to control speed with bits 0-3 being defined exactly as in S-9.2 Section B. If Bit 1 of CV 29 has a value of one (1), then bit 4 is used as an intermediate speed step, as defined in S-9.2, Section B. If Bit 1 of CV 29 has a value of zero (0), then bit 4 shall be used to control FL [3]. In this mode, Speed U0000 is stop, speed U0001 is emergency stop, speed U0010 is the first speed step and speed U1111 is full speed. This provides 14 discrete speed steps in each direction. If a decoder receives a new speed step that is within one step of current speed step, the Digital Decoder may select a step half way between these two speed steps. This provides the potential to control 56 speed steps should the command station alternate speed packets. Decoders may ignore the direction information transmitted in a broadcast packet for Speed and Direction commands that do not contain stop or emergency stop information. When operations mode acknowledgement is enabled, receipt of any speed and direction packet must be acknowledged with an operations mode acknowledgement.

Function Group One Instruction (100) [4]

The format of this instruction is:

100DDDDD

Up to 5 auxiliary functions (functions FL and F1-F4) can be controlled by the Function Group One instruction. Bits 0-3 shall define the value of functions F1-F4 with function F1 being controlled by bit 0 and function F4 being controlled by bit 3. A value of 1 shall indicate that the function is “on” while a value of 0 shall indicate that the function is “off”. If Bit 1 of CV 29 has a value of one (1), then bit 4 controls function FL, otherwise bit 4 has no meaning.

When operations mode acknowledgment is enabled, receipt of a function group 1 packet must be acknowledged according with an operations mode acknowledgement.

Function Group Two Instruction(101) [5]

The format of this instruction is:

101SDDDD

Up to 8 additional auxiliary functions (F5-F12) can be controlled by a Function Group Two instruction. Bit 4 defines the use of Bits 0-3. When bit 4 (S) is 1, Bits 0-3 (DDDD) shall define the value of functions F5-F8 with function F5 being controlled by bit 0 and function F8 being controlled by bit 3. When bit 4 (S) is 0, Bits 0-3 (DDDD) shall define the value of functions F9-F12 with function F9 being controlled by bit 0 and function F12 being controlled by bit 3. A value of 1 hall indicate that the function is “on” while a value of 0 shall indicate that the function is “off”.

When operations mode acknowledgment is enabled, receipt of function group 2 packet shall be acknowledged according with an operations mode acknowledgement.

Feature Expansion Instruction (110)

The instructions in this group provide for support of additional features within decoder (See TN-3-05).

The format of two byte instructions in this group is:

110CCCCC 0 DDDDDDDD

The format of three byte instructions in this group is:

110CCCCC 0 DDDDDDDD 0 DDDDDDDD

The 5-bit sub-instruction CCCCC allows for 32 separate Feature Expansion Sub-instructions.

CCCCC	Description
00000	Binary State Control Instruction - Long Form
11101	Binary State Control Instruction - Short Form
11110	F13-F20 Function Control
11111	F21-F28 Function Control

Binary State Control Instruction - Long Form

Sub instruction 00000 is a three byte instruction and provides for control of one of 32767 binary states within the decoder. The two bytes following this instruction byte have the format DLLLLLLL 0 HHHHHHHH. Bits 0-6 of the first data byte (LLLLLLL) shall define the low order bits of the binary state address; bits 0-7 of the second data byte (HHHHHHHH) shall define the high order bits of binary state address. The addresses range from 1 to 32767. Bit 7 of the second byte (D) defines the binary state. A value of 1 shall indicate that the binary state is “on” while a value of 0 shall indicate that the binary state is “off”. The value of 0 for the address is reserved as broadcast to clear or set all 32767 binary states. An instruction 11000000 0 00000000 0 00000000 sets all 32767 binary states to off.

Binary states accessed with all high address bits set to zero would be the same as accessed by the short form of the binary state control. Command stations shall use the short form in this case, i.e. Binary State Controls 1 to 127 should always be addressed using the short form. Decoders supporting the long form shall support the short form as well.

Binary State Control Instruction - Short Form

Sub-instruction 11101 is a two byte instruction and provides for control of one of 127 binary states within the decoder. The single byte following this instruction byte has the format DLLLLLLL. Bits 0-6 of the second byte (LLLLLLL) shall define the number of the binary state starting with 1 and ending with 127. Bit 7 (D) defines the binary state. A value of 1 shall indicate the binary state is “on” while a value of 0 shall indicate the binary state is “off”. The value of 0 for LLLLLLL is reserved as broadcast to clear or set all 127 binary states accessible by the short form of the binary state control. An instruction 11011101 0 00000000 sets all 127 binary states accessed by this instruction to off.

Binary State Controls are quite similar to Functions, as they may control any output, sound or any other feature of digital nature within a decoder in direct response to a packet received. But Binary State Controls do have a different access method and function space. Therefore they have a different name.

Binary state control packets – both short and long form – will not be refreshed. Therefore non-volatile storage of the function status is suggested. When operations mode acknowledgment is enabled, receipt of a Binary State Control packet shall be acknowledged accordingly with an operations mode acknowledgment. Consult the Technical Note(s) for additional information on this instruction (See TN-4-05).

F13-F20 Function Control

Sub-instruction 11110 is a two byte instruction and provides for control of eight (8) additional auxiliary functions F13-F20. The single byte following this instruction byte indicates whether a given function is turned on or off, with the least significant bit (Bit 0) controlling F13, and the most significant bit (bit 7) controlling F20. A value of 1 in D for a given function shall indicate the function is “on” while a value of 0 in D for a given function shall indicate a given function is “off”. It is recommended, but not required, that the status of these functions be saved in decoder storage such as NVRAM. It is not required, and should not be assumed that the state of these functions is constantly refreshed by the command station. Command Stations that generate these packets, and which are not periodically refreshing these functions, must send at least two repetitions of these commands when any function state is changed. When operations mode acknowledgment is enabled, receipt of an F13-F20 Function Control packet shall be acknowledged accordingly with an operations mode acknowledgement. Consult the Technical Note(s), TN-4-05, for additional information on this instruction.

F21-F28 Function Control

Sub-instruction 11111 is a two byte instruction and provides for control of eight (8) additional auxiliary functions F21-F28. The single byte following this instruction byte indicates whether a given function is turned on or off, with the least significant bit (Bit 0) controlling F21, and the most significant bit (bit 7) controlling F28. A value of 1 in D for a given function shall indicate the function is “on” while a value of 0 in D for a given function shall indicate a given function is “off”. It is recommended, but not required that the status of these functions be saved in decoder storage such as NVRAM. It is not required, and should not be assumed that the state of these functions is constantly refreshed by the command station. Command Stations that generate these packets, and which are not periodically refreshing these functions, must send at least two repetitions of these commands when any function state is changed. When operations mode acknowledgment is enabled, receipt of an F21-F28 Function Control packet shall be acknowledged accordingly with an operations mode acknowledgement. Consult the Technical Note(s), TN-4-05, for additional information on this instruction.

The remaining 28 sub-instructions are reserved by the NMRA for future use [6].

Configuration Variable Access Instruction (111)

The Configuration Variable Access instructions are intended to set up or modify Configurations Variables either on the programming track or on the main line. There are two forms of this instruction. The short form is for modifying selected frequently modified Configuration Variables. The long form is for verifying or modifying any selected Configuration Variable. Only a single configuration variable access instruction may be contained in a packet.

Configuration Variable Access Acknowledgment

If a configuration variable access acknowledgment is required, and the decoder has decoder operations-mode acknowledgment enabled, the decoder shall respond with an operations mode acknowledgment.

Configuration Variable Access Instruction - Short Form

The format of this instruction is:

1111CCCC 0 DDDDDDDD

The 8 bit data DDDDDDDD is placed in the configuration variable identified by CCCC according to the following table.

CCCC	Description
0000	Not available for use
0010	Acceleration (CV 23)
0011	Deceleration (CV 24)
1001	See S-9.2.3, Appendix B

The remaining values of CCCC are reserved and will be selected by the NMRA as need is determined.

Only a single packet is necessary to change a configuration variable using this instruction. If the decoder successfully receives this packet, it shall respond with an operations mode acknowledgment.

Configuration Variable Access Instruction - Long Form

The long form allows the direct manipulation of all CVs [7]. This instruction is valid both when the Digital Decoder has its long address active and short address active. Digital Decoders shall not act on this instruction if sent to its consist address. The format of the instructions using Direct CV addressing is:

1110CCVV 0 VVVVVVVV 0 DDDDDDDD

The actual Configuration Variable desired is selected via the 10-bit address with the 2-bit address (VV) in the first data byte being the most significant bits of the address. The Configuration variable being addressed is the provided 10-bit address plus 1. For example, to address CV 1 the 10 bit address is 00 00000000.

The defined values for Instruction type (CC) are:

CC	Description
00	Reserved for future use
01	Verify byte
11	Write byte
10	Bit manipulation

Verify Byte

The contents of the Configuration Variable as indicated by the 10-bit address are compared with the data byte (DDDDDDDD). If the decoder successfully receives this packet and the values are identical, the Digital Decoder shall respond with the contents of the CV as the Decoder Response Transmission, if enabled.

Write Byte

The contents of the Configuration Variable as indicated by the 10-bit address are replaced by the data byte (DDDDDDDD). Two identical packets are needed before the decoder shall modify a configuration variable [8]. These two packets need not be back to back on the track. However any other packet to the same decoder will invalidate the write operation. (This includes broadcast packets.) If the decoder successfully receives this second identical packet, it shall respond with a configuration variable access acknowledgment.

Bit Manipulation

The bit manipulation instructions use a special format for the data byte (DDDDDDDD):

111CDBBB

Where BBB represents the bit position within the CV, D contains the value of the bit to be verified or written, and C describes whether the operation is a verify bit or a write bit operation.

C	Description
1	Write bit
0	Verify bit

The Verify Bit and Write Bit instructions operate in a manner similar to the Verify Byte and Write Byte instructions (but operates on a single bit). Using the same criteria as the Verify Byte instruction, an operations mode acknowledgment will be generated in response to a Verify Bit instruction if appropriate. Using the same criteria as the Write Byte instruction, a configuration variable access acknowledgment will be generated in response to the second identical Write Bit instruction if appropriate.

D: Accessory Digital Decoder Packet Formats

Accessory Digital Decoders are intended for control of a number of simple functions such as switch machine control or turning on and off lights. It is permissible to develop Digital Decoders that respond to multiple addresses so that more devices can be controlled by a single Digital Decoder.

Basic Accessory Decoder Packet Format

The format for packets intended for Accessory Digital Decoders is:

preamble 0 10AAAAAA 0 1AAACDDD 0 EEEEEEEE 1

Accessory Digital Decoders can be designed to control momentary or constant-on devices, the duration of time each output is active being controlled by configuration variables CVs 515 through 518. Bit 3 of the second byte C is used to activate or deactivate the addressed device. (Note if the duration the device is intended to be on is less than or equal the set duration, no deactivation is necessary.) Since most devices are paired, the convention is that bit 0 of the second byte is used to distinguish between which of a pair of outputs the accessory decoder is activating or deactivating. Bits 1 and 2 of byte two are used to indicate which of 4 pairs of outputs the packet is controlling. The most significant bits of the 9-bit address are bits 4-6 of the second data byte. By convention these bits (bits 4-6 of the second data byte) are in ones’ complement.

If operations-mode acknowledgement is enabled, receipt of a basic accessory decoder packet must be acknowledged with an operations-mode acknowledgement.

Extended Accessory Decoder Control Packet Format

The Extended Accessory Decoder Control Packet is included for the purpose of transmitting aspect control to signal decoders or data bytes to more complex accessory decoders. Each signal head can display one aspect at a time.

preamble 0 10AAAAAA 0 0AAA0AA1 0 000XXXXX 0 EEEEEEEE 1

XXXXX is for a single head. A value of 00000 for XXXXX indicates the absolute stop aspect. All other aspects represented by the values for XXXXX are determined by the signaling system used and the prototype being modeled.

If operations-mode acknowledgement is enabled, receipt of a basic accessory decoder packet must be acknowledged with an operations-mode acknowledgement.

Broadcast Command for Accessory Decoders

Broadcast Command for Basic Accessory Decoders

The format for the broadcast instruction is

preamble 0 10111111 0 1000CDDD 0 EEEEEEEE 1

This packet shall be executed by all accessory decoders. CDDD is defined as specified in the paragraph on Basic Accessory Decoder Packet Format.

Broadcast Command for Extended Accessory Decoders

The format for the broadcast instruction is:

preamble 0 10111111 0 00000111 0 000XXXXX 0 EEEEEEEE 1

All extended accessory decoders must execute this packet. XXXXX is defined as specified in the paragraph on Extended Accessory Decoder Packet Format.

Accessory Decoder Configuration Variable Access Instruction

Accessory decoders can have their Configuration variables changed in the same method as locomotive decoders using the Configuration Variable Access Instruction - Long Form instruction defined above. For the purpose of this instruction, the accessory decoders’ address is expanded to two bytes in the following method. If operations470 mode acknowledgement is enabled, the receipt of an Accessory Decoder Configuration Variable Access instruction must be acknowledged in the same manner as the Configuration Variable Access Instruction – Long Form.

Basic Accessory Decoder Packet address for operations mode programming

10AAAAAA 0 1AAACDDD

Where DDD is used to indicate the output whose CVs are being modified and C = 1. If CDDD = 0000 then the CVs refer to the entire decoder. The resulting packet would be:

preamble 10AAAAAA 0 1AAACDDD 0 1110CCVV 0 VVVVVVVV 0 DDDDDDDD 0 EEEEEEEE 1
         Accessory Decoder Address                              Error Byte
                               Configuration Variable Access Instruction

Extended Decoder Control Packet address for operations mode programming

10AAAAAA 0 0AAA0AA1

Please note that the use of 0 in bit 3 of byte 2 is to ensure that this packet cannot be confused with the legacy accessory-programming packets. The resulting packet would be:

preamble 10AAAAAA 0 0AAA0AA1 0 1110CCVV 0 VVVVVVVV 0 DDDDDDDD 0 EEEEEEEE 1
         Signal Decoder Address                                 Error Byte
                               Configuration Variable Access Instruction

E: Operations Mode Acknowledgment

The operations-mode acknowledgement mechanism as defined in S-9.3.1 and S-9.3.2 are the only valid acknowledgement in operations mode. Whenever an acknowledgement is requested, the decoder shall respond using this mechanism described in S-9.3.1 and S-9.3.2.

Appendix A

This Appendix contains additional useful information and/or legacy instructions. A DCC product need not implement any items described in this appendix.

Accessory Decoder Configuration Variable Access Instruction [9]

The following command is included for backward compatibility for some older accessory decoders. Its use is discouraged in new decoder designs.

The format for Accessory Decoder Configuration Variable Access Instructions is:

preamble 0 10AAAAAA 0 0AAA11VV 0 VVVVVVVV 0 DDDDDDDD 0 EEEEEEEE 1

Where:

Symbol	Description
A	Decoder address bits
V	Desired CV address - (CV 513 = 10 00000000)
D	Data for CV

The bit patterns described by VV VVVVVVVV in the second and third bytes and DDDDDDDD in the fourth byte are also identical to the corresponding bits in the Configuration Variable Access Instruction - Long Form (see S520 9.2.1).

The purpose of this instruction is to provide a means of programming all parameters of an accessory decoder after it is installed on the layout. It is recommended that Command Stations exercise caution if changes to the address (CV 513 and CV 521) are allowed.

Footnotes

[1]

This instruction also applies to accessory decoders.

[2]

In 128 speed step mode, the maximum restricted speed is scaled from 28 speed mode.

[3]

FL is used for the control of the headlights.

[4]

Any function in this packet group may be directionally qualified.

[5]

Any function in this packet group may be directionally qualified.

[6]

The NMRA shall not issue a NMRA Conformance Warrant for any product that uses an instruction or subinstruction that has been reserved by the NMRA.

[7]

Because of the length of this instruction, care must be taken to ensure that the maximum time between packets is not exceeded.

[8]

Note that CV 17 and CV 18 are a “paired CV”. A “paired CV” refers to a pair of CVs which taken together hold one piece of data. A Write Byte instruction to CV17 will take effect only when CV18 is written. Other paired CVs will work in a similar manner. See S-9.2.2 Configuration Variables For Digital Command Control for more information on paired CVs.

[9]

For backward compatibility, decoders should check the length of instruction packets when bit 7 of byte 2 is zero.